The present invention relates to analog front end (AFE) circuits for use in high-speed communications systems. In particular, the present invention is directed to AFEs having a number of parallel stages, each of which processes a fractional portion (frequency band) of a wideband signal by filtering, modulating, and converting such portion into a series of digital data samples. The present invention has particular applicability to ADSL modem environments.
To provide high bit rate transmission over existing telephone subscriber loops, various modem technologies have been proposed. One of the promising solutions is the T1E1.4 Asymmetric Digital Subscriber Loop (ADSL) standard based on the Discrete Multiple Tone (DMT) technology. This standard provides up to 6.144 Mb/s transmission from the central office to a subscriber (downstream) and up to 640 kb/s transmission from the subscriber to the central office (upstream). To achieve this high bit rate transmission over existing telephone subscriber loops, advanced analog front end (AFE) devices, digital signal processing techniques, and high-speed complex digital designs are required. As a result, this pushes the current technology limit and imposes both high dollar cost and power consumption.
Among the technical challenges, AFE devices in modem applications provide the interface between the analog wave forms and the digital samples for digital hardware/software processing. In high-speed modem technologies such as ADSL, AFE devices need to operate at a very high sampling rate and high accuracy. For example, DMT technology has a signal spectrum of 1.1 MHz and requires sampling above 50 MHz if the sigma-delta analog-to-digital (ADC) method is used. This thus requires state-of-art ADC technology and imposes a high cost.
In addition to the speed requirement, the time domain signal in ADSL/DMT transmission is a summation of a large number of carriers modulated by a quadrature amplitude modulation (QAM) method. This results in a large peak-to-peak deviation. As a result, a large dynamic range and high resolution ADC is required to minimize quantization error.
There is prior art that uses multiple sigma-delta modulators to avoid high-speed quantization and its associated cost and consequences. One approach is proposed by P. Aziz, H. V. Sorensen, and J. Van del Spiegel who published a paper titled xe2x80x9cMulti Band Sigma Delta analog to Digital Conversionxe2x80x9d in the International Conference on Acoustics, Speech and Signal Processing, pp. III-249, Apr. 19-22, 1994. In this technique, sample-and-hold and quantization operations are performed in two blocks. Each sigma-delta modulator is different and operates on a different frequency band. Each sigma-delta modulator is followed by a corresponding Finite Impulse Response (FIR) filter to reject out-of-band noise. This approach is useful in some contexts, but suffers from various drawbacks, including: (1) requiring different FIR implementations, and (2) ineffective quantization noise reduction. But most importantly, it still requires high-speed sampling of the incoming signal.
A second approach is suggested by I. Galton and H. T. Jensen and disclosed in IEEE Transcations on Circuits and Systems, II, Analog and Digital Signal Processing, vol. 42, no. 12, p. 773, December 1995. Like Aziz et al., this disclosure shows that the sampling-and-hold and quantization are separated into two blocks. A Hadamard sequence is used to multiply the sampled signals before and after the sigma-delta quantization. From this scheme, the number of parallel sigma-delta modulators cannot be arbitrary due to the construction of Hadamard sequences, which makes it unattractive for systems that are designed to be upgraded easily and flexibly. Furthermore, it suffers the same limitation of high-speed sampling.
Another approach is proposed by R. Khoini-Poorfard and D. A. Johns and disclosed in IEE Electronics Letters, vol. 29, no. 19, p. 1673, September 1993. As with the other approaches, the sampling-and-hold and quantization is separated in two blocks. In this scheme, it divides the sampled sequence into different bit streams in the time domain and quantizes by different sigma-delta modulators to achieve the same effect of quantization noise reduction. Again, this technique requires high-speed sampling which is undesirable.
Accordingly, one object of the present invention is to provide a flexible and upgradeable solution to convert wideband signals to high resolution digital signals such as are found in typical high-speed ADSL communications systems;
A further objective of the present invention is to provide an analog front end receiving circuit having reduced quantization errors and reduced quantization noise, so that the performance of a communications system employing such circuit can be enhanced
A further objective of the present invention is to reduce the sampling rate required in an analog front end receiving circuit, so that the conversion of a wideband analog signal to a high resolution digital signals can be accomplished with simpler and less costly Sigma-Delta modulators.
These objects and others are accomplished by providing a high speed communications transceiver which includes a novel front end receiving circuit for performing filtering and analog to digital conversion on a wideband analog data signal. The front end receiving circuit includes a number of stages that: (i) divide the wideband signal into a plurality of sub-bands, such that each sub-band includes data from a frequency band which is a fractional portion of the bandwidth of the wideband signal; and (ii) sample the sub-bands and generate digital signals corresponding to data carrying signals within such sub-band. A conventional signal processing circuit then extracts the received digital data from the digital signals from each of the plurality of sub-bands. The present invention is also compatible with software modem implementations in which the signal processing (or data pump) is located within a user host processing device instead of onboard the transceiver.
In a preferred ADSL embodiment, N sub-band filters in the front end circuit divide the analog data signal into N filtered analog data signals occupying N different frequency bands. To facilitate manufacture and flexible operation, the N frequency bands are chosen to be approximately equal to a frequency bandwidth size f, where f less than F, and where F=N*f. The division of the input signal into multiple sub-bands has the added advantage of reducing clipping noise, and enables the use of lower speed sampling (instead of Nyquist sampling) analog to digital converters. Again in a preferred embodiment, the N sub-band filters are arranged in parallel stages which operate simultaneously on different frequency portion k*f of said analog signal, where k={0, 1, 2, 3, . . . Nxe2x88x921}. Further in a preferred embodiment, N is selected to be 2, 4, or 8, and f is approximately 138 khz, so that in a DMT environment, 32 subchannels are processed by each AFE stage.
A major contribution of the present invention lies in the reduction of quantization noise achievable in an ADSL transceiver which comes about as a result of baseband modulating the analog data signals after they are filtered to generate N frequency shifted (baseband) analog data signals. In such an implementation, N substantially identical Sigma Delta modulators and N filters can be used to effectuate an analog to digital conversion of the analog baseband signals.
The entire front end receiving circuit (or portions thereof, such as the sub-band stages) can be implemented in modular form such as in an integrated circuit. In this manner, front ends with varying performance can be conveniently fabricated and placed into communications systems with varying communications requirements. This also means that the receiving circuit of an ADSL modem employing the present invention can be upgraded in functionality easily and economically, and without affecting the remainder of a communications system.
In another variation of the invention, the front end receiving circuit can be made programmable, so that it can be dynamically configured by a control circuit to perform filtering and analog to digital conversion on input signals of varying bandwidth.
Another inventive aspect of the present disclosure includes a new distribution circuit, which is coupled to the transceiver and distributes the extracted data to one or more host processing systems. This circuit also controls the analog front end stages of the transceiver, so that the entire downstream data transmission can be broken up into virtual data ports that can be shared by a number of users. The allocation of data, therefore, contained in the DMT subchannels can be configured, controlled, and adjusted based on the bandwidth requirements and needs of such users in a xe2x80x9cpoolingxe2x80x9d arrangement heretofore unavailable for ADSL environments.
One distinct advantage of using sigma-delta modulators as disclosed in the present invention, in contrast to regular Nyquist rate analog-to-digital (ADC) converters, is in the shaping of quantization noise, which is reduced in a low frequency band and increased in a high frequency band. By using a low pass FIR filter after sigma-delta modulation, the quantization noise can be greatly reduced using the present invention. Therefore, to take advantage of this uniqueness for ADSL/DMT applications, some pre-processing is used to shift different ADSL/DMT signal bands to baseband. Because fewer data samples are created by the AFE, a FFT stage in the DMT Rx core can also be reduced in size, complexity, and cost.
Although the inventions are described below in a preferred embodiment implementing the ADSL T1E1.413 standard, it will be apparent to those skilled in the art the present invention would be beneficially used in any high-speed rate-adaptable applications.